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Version 2 Schematic under development
| From: | Jim Brain (brain) | (Tue Jun 21 17:50:48 2005) |
| The RAM and latch are not absolutely required, but the 4kB of internal CPU RAM will only support 4-5 open file buffers. More elaborate usage will require external RAM. | ||
| From: | Jim Brain (brain) | (Tue Jun 21 17:52:00 2005) |
| SV1 is a RapiDOS/SpeedDOS compliant parallel transfer connector. Later on, the firmware to support such a cable could be added. I think 500kBps - 1MBps transfers are possible. | ||
| From: | Jim Brain (brain) | (Tue Jun 21 17:53:01 2005) |
| The bulky DIN IEC connectors were discarded in favor of the header. If I have room over, I'll add the connector footprint back in. | ||
| From: | Jim Brain (brain) | (Tue Jun 21 17:54:38 2005) |
| I routed the SRQ line to the CPU shift register, to allow burst support to be added to the firmware. Currently, as with parallel transfers, firmware support is missing. | ||
| From: | Raymond Day | (Wed Jun 22 08:27:21 2005) |
| I did not know you made this thinking of other things to add. Sounds good that you did that. But when do you think you will have all the info. put up so people can do it them selfs? | ||
| From: | Raymond Day | (Wed Jun 22 08:31:25 2005) |
| I was thinking you all most had this done at the Expo how you showed it, it was working good. I guess it's like still in bata and you want to do more work before you put up the info. for others to do it. Thank you. | ||
| From: | Jim Brain (brain) | (Wed Jun 22 11:25:16 2005) |
| Even as I brought the unit to EXPO, I knew it needed work. For instance, the current version can only have 1 file open, which prevent file to file copies, etc. So, yes, the unit was but just a alpha unit. | ||
| From: | Raymond Day | (Thu Sep 22 10:11:38 2005) |
| In this you don't have what type of chip IC3 is? | ||
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